compilers¶

class SynthDefCompiler¶

Bases: object

static compile_parameters(synthdef)¶

static compile_synthdef(synthdef, name)¶

static compile_synthdefs(synthdefs, use_anonymous_names=False)¶

static compile_ugen(ugen, synthdef)¶

static compile_ugen_graph(synthdef)¶

static compile_ugen_input_spec(input_, synthdef)¶

static encode_float(value)¶

static encode_string(value)¶

static encode_unsigned_int_16bit(value)¶

static encode_unsigned_int_32bit(value)¶

static encode_unsigned_int_8bit(value)¶

class SynthDefDecompiler¶

Bases: object

SynthDef decompiler.

>>> import supriya.synthdefs
>>> import supriya.ugens
>>> with supriya.synthdefs.SynthDefBuilder(
...     frequency=440,
...     trigger=supriya.synthdefs.Parameter(
...         value=0.0,
...         parameter_rate=supriya.enums.ParameterRate.TRIGGER,
...     ),
... ) as builder:
...     sin_osc = supriya.ugens.SinOsc.ar(frequency=builder["frequency"])
...     decay = supriya.ugens.Decay.kr(
...         decay_time=0.5,
...         source=builder["trigger"],
...     )
...     enveloped_sin = sin_osc * decay
...     out = supriya.ugens.Out.ar(bus=0, source=enveloped_sin)
... 
>>> synthdef = builder.build()
>>> supriya.graph(synthdef)  

>>> print(synthdef)
synthdef:
    name: 001520731aee5371fefab6b505cf64dd
    ugens:
    -   TrigControl.kr: null
    -   Decay.kr:
            source: TrigControl.kr[0:trigger]
            decay_time: 0.5
    -   Control.kr: null
    -   SinOsc.ar:
            frequency: Control.kr[0:frequency]
            phase: 0.0
    -   BinaryOpUGen(MULTIPLICATION).ar:
            left: SinOsc.ar[0]
            right: Decay.kr[0]
    -   Out.ar:
            bus: 0.0
            source[0]: BinaryOpUGen(MULTIPLICATION).ar[0]

>>> compiled_synthdef = synthdef.compile()
>>> sdd = supriya.synthdefs.SynthDefDecompiler
>>> decompiled_synthdef = sdd.decompile_synthdefs(compiled_synthdef)[0]
>>> supriya.graph(decompiled_synthdef)  

>>> print(decompiled_synthdef)
synthdef:
    name: 001520731aee5371fefab6b505cf64dd
    ugens:
    -   TrigControl.kr: null
    -   Decay.kr:
            source: TrigControl.kr[0:trigger]
            decay_time: 0.5
    -   Control.kr: null
    -   SinOsc.ar:
            frequency: Control.kr[0:frequency]
            phase: 0.0
    -   BinaryOpUGen(MULTIPLICATION).ar:
            left: SinOsc.ar[0]
            right: Decay.kr[0]
    -   Out.ar:
            bus: 0.0
            source[0]: BinaryOpUGen(MULTIPLICATION).ar[0]

>>> str(synthdef) == str(decompiled_synthdef)
True

static decompile_synthdef(value)¶

static decompile_synthdefs(value)¶